module RF(Read1, Read2, Data1, Data2, Write, WriteData, RegWrite, Clk, RESET);
	input [4:0] Read1, Read2, Write; 
	input [7:0] WriteData;
	input RegWrite, Clk, RESET;
	output [7:0] Data1, Data2;
	
	wire [7:0] D[31:0];
	wire [7:0] Q[31:0];
	
	wire [31:0] Qt[7:0]; //transposed Q, for mux32to1
	
	wire [31:0] decoderResult;
	
	genvar i, j;
	
	Decoder_5to32 Decoder_WhichtoWrite(.A(Write), .D(decoderResult));
	
	assign Q[0]=8'b0;
	
	generate
		for(i=1;i<32;i=i+1)
		begin : REGs
			MUX_2to1 #(8) REGin(.D0(Q[i]), .D1(WriteData), .S0(RegWrite&decoderResult[i]), .Y(D[i]));
			/*
			for(j=0;j<8;j=j+1)
			begin : DFFs2
				D_FF Ds(.D(D[i][j]), .C(Clk), .Q(Q[i][j]), .RESET(RESET));
			end
			*/
			register_customsize #(8) Regs(.D(D[i]), .C(Clk), .Q(Q[i]), .RESET(RESET));
			
		end
	endgenerate
	
	//generate transpose Q
	generate
		for(i=0;i<32;i=i+1)
		begin : generateQt
			for(j=0;j<8;j=j+1)
			begin : generateQt2
				assign Qt[j][i]=Q[i][j];
			end
		end
	endgenerate
	
	
	generate
		for(j=0;j<8;j=j+1)
		begin : Reads
			MUX_32to1 Read1Mux(.D(Qt[j]), .S(Read1), .Y(Data1[j]));
			MUX_32to1 Read2Mux(.D(Qt[j]), .S(Read2), .Y(Data2[j]));
		end
	endgenerate
	

	
endmodule